`include "defines.v"

module ctrl (

    input wire                  rst,

    input wire                  flush_flag_from_exe_i,

    input wire                  stall_flag_from_id_i,

    input wire                  csr_transfer_flag,

    output wire[4:0]            stall_o,
    output wire[4:0]            flush_o
);

    /*******************
    index:  4       3       2       1       0
            pc      if/id   id/exe  exe/mem mem/wb
    *******************/
    assign stall_o = stall_flag_from_id_i  ? 5'b11000 : 5'b00000;

    //flush_flag_from_exe_i 与 stall_flag_from_id_i同一时间只能发生一个，所以顺序无所谓
    assign flush_o = csr_transfer_flag     ? 5'b01111 :
                     flush_flag_from_exe_i ? 5'b01100 : 
                     stall_flag_from_id_i  ? 5'b00100 : 5'b00000;
                    
endmodule